1. Field of the Invention
This invention generally relates to electronic circuits and, more particularly, to a latch isolation system using passive component switches.
2. Description of the Related Art
As noted in Wikipedia, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and has one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered).
FIG. 1 is a schematic diagram of a D flip-flop (prior art). There are a number of latch types known in the art. One widely used device is the D flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the falling edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change.
FIG. 2A is a schematic diagram depicting a conventional latch circuit (prior art). The differential inputs (INP, INN) are sampled after subtracting the reference voltages (RP, RN) from their respective inputs. The result of the subtraction (CP, CN) is fed to the differential latch input (LP, LN). A pre-amplifier 202 is used to reduce offset and to isolate the latch 200, and prevent the latch from feeding signals back into the input nodes (INP, INN).
FIG. 2B is a plot depicting two non-overlapping clock phases, PH2 and PH1 associated with the circuit of FIG. 2B (prior art). The timing relationship between the two phases is shown. During PH2, the reference voltage is sampled onto the capacitors C1 and C2. During PH1, input voltage is connected to SP and SN. Also during PH1, the difference between the input (INP, INN) and the reference (RP, RN) appears at the pre-amplifier input (CP, CN). The pre-amplifier then buffers its input and feeds it to the latch (LP, LN). At the end of the PH1 pulse, the latch is activated and generates a digital signal (DP, DN) to represent the latch input (LP, LN). While the circuit of FIG. 2A provides latch isolation, the use of a pre-amplifier is costly in terms of space and power usage.
It would be advantageous if a latch could be adequately isolated without the use of a pre-amplifier.